A semiconductor vision beyond the factory floor
The Union Cabinet has approved the second phase of the India Semiconductor Mission (ISM 2.0) with a proposed outlay of approximately ₹1.27 lakh crore (about $13.21 billion), a substantial expansion over the ₹76,000 crore outlay of ISM 1.0 (2021)
ISM 2.0 broadens government support beyond wafer fabrication and packaging to cover semiconductor equipment, materials, indigenous intellectual property, chip design, talent development and supply-chain resilience, with a stated target of around 75% domestic self-sufficiency in semiconductor demand by 2030
India's semiconductor ecosystem has developed across three layers in under four years: a fabless design layer (Design Linked Incentive-supported startups plus global capability centres of multinationals), a packaging/testing (OSAT/ATMP) layer with multiple facilities operational or under construction in Gujarat and Assam, and a wafer fabrication layer led by the Tata Electronics-PSMC plant at Dholera
A key policy question raised is whether these three layers are functionally integrated — specifically, whether upcoming fab and packaging capacity will be priced and specified to serve domestic fabless design companies, rather than operating as three disconnected value chains each oriented toward export or foreign clients
India Semiconductor Mission (ISM)
The India Semiconductor Mission is the nodal programme for building India's semiconductor and display manufacturing ecosystem. It was approved by the Union Cabinet in December 2021 under the Ministry of Electronics and Information Technology (MeitY) with a financial outlay of ₹76,000 crore. Institutionally, ISM operates as an independent Business Division within the Digital India Corporation, with delegated administrative and financial powers, supported by an advisory board of global semiconductor industry experts.
Key Details
- Launched: December 2021; nodal ministry: MeitY
- Original (ISM 1.0) outlay: ₹76,000 crore
- Governing body: Digital India Corporation (an independent business division), not a separate statutory authority
- Mandate covers three pillars: semiconductor fabrication, display fabrication, and ATMP/OSAT (Assembly, Testing, Marking and Packaging)
ISM 2.0 is the scaled-up successor to this original mission, extending its scope from capital-intensive fabs toward the design and materials layers of the value chain.
ISM 2.0 and Approved Fab/OSAT Projects
Under ISM 1.0, six projects were approved with a combined committed investment exceeding ₹1.6 lakh crore. These include the Tata Electronics-Powerchip Semiconductor Manufacturing Corporation (PSMC) fab at Dholera, Gujarat (a 28nm-capable fab, ₹91,000 crore investment, targeted capacity of 50,000 wafers/month); Micron Technology's ATMP plant at Sanand, Gujarat ($2.75 billion, approved June 2023 — the first ISM-supported facility to break ground); the CG Power-Renesas-Stars Microelectronics OSAT facility at Sanand (₹7,600 crore, focused on power-management ICs); Tata Electronics' OSAT unit in Jagiroad, Assam (₹27,000 crore, targeted capacity of up to 48 million chips/day for automotive and EV applications); a Kaynes Technology unit at Sanand; and an HCL-Foxconn display-driver IC fab at Jewar, Uttar Pradesh.
Key Details
- Total committed investment across six ISM 1.0-approved projects: over ₹1.6 lakh crore
- Tata-PSMC Dholera fab: first silicon targeted for December 2026, full production by 2028
- ISM 2.0 will additionally provide a 30% incentive for semiconductor equipment, chemicals, gases and materials manufacturers, and support chip design through grants and equity investment
These facilities constitute the "factory floor" — the fabrication and packaging capacity — while ISM 2.0's broadened scope is aimed at building the surrounding ecosystem (design, materials, talent, IP) that determines whether this capacity translates into a self-reliant semiconductor industry.
Design Linked Incentive (DLI) Scheme
The Design Linked Incentive Scheme, notified in 2021 under ISM, supports the fabless chip-design segment of the value chain through two components. The Chip Design Infrastructure component provides subsidized access to Electronic Design Automation (EDA) tools. The Product Design Linked Incentive (P-DLI) reimburses up to 50% of eligible expenditure on design, testing and demonstration (manpower, EDA software licences, IP registration, prototype validation), capped at ₹15 crore per project. The Deployment Linked Incentive (DLI) rewards commercialisation, offering 4–6% of net sales of the designed product over five years, capped at ₹30 crore per applicant. C-DAC (Centre for Development of Advanced Computing) is the nodal implementing agency.
Key Details
- P-DLI reimbursement: up to 50% of eligible expenditure, ceiling ₹15 crore per project
- Deployment-linked incentive: 4–6% of net sales, ceiling ₹30 crore per applicant, over 5 years
- Nodal implementing agency: C-DAC
- As of 2026: 24 projects supported under DLI, 105 companies given access to advanced chip-design tools, 23 tapeouts completed
The DLI scheme is the primary instrument for the "design" layer of the ecosystem — the layer the editorial vision argues must be commercially connected to the fab and OSAT capacity being built, rather than developing in isolation.
Semiconductor Value Chain: Fab, OSAT/ATMP and Fabless Design
A semiconductor value chain has three broad functional layers. A fab (wafer fabrication plant) manufactures the actual silicon chips from raw wafers using photolithography. OSAT/ATMP (Outsourced Semiconductor Assembly and Test / Assembly, Testing, Marking and Packaging) units take fabricated dies and package, test and mark them into usable chip components — a less capital-intensive but still specialised stage. Fabless design companies design chips (ICs, SoCs) without owning fabrication capacity, instead outsourcing manufacturing to foundries; this is the segment served by the DLI scheme and by global capability centres of multinational chip firms located in India.
Key Details
- India currently has three OSAT units commercially operational in Gujarat, with more under construction
- The fabless/design layer includes DLI-supported startups plus over 50 global capability centres of multinational semiconductor firms operating design work out of India
- A functioning domestic ecosystem requires commercial linkages between all three layers — i.e., domestically fabricated and packaged chips being priced and specified for domestic fabless design firms, not solely routed to export or foreign clients
This three-layer framework is the analytical basis for evaluating whether India's semiconductor policy has moved "beyond the factory floor" — i.e., whether fabrication investment is being matched by ecosystem-level integration across design, materials and packaging.
- ISM 1.0 outlay: ₹76,000 crore (approved December 2021, MeitY)
- ISM 2.0 outlay: approximately ₹1.27 lakh crore (~$13.21 billion)
- ISM 1.0 approved projects: 6, combined committed investment over ₹1.6 lakh crore
- Tata-PSMC Dholera fab: ₹91,000 crore, 28nm node, 50,000 wafers/month capacity target
- Micron Sanand ATMP: $2.75 billion, approved June 2023
- DLI scheme: P-DLI reimbursement up to 50% (cap ₹15 crore); deployment incentive 4–6% of net sales (cap ₹30 crore); nodal agency C-DAC
- DLI scheme progress: 24 projects supported, 105 companies with EDA tool access, 23 tapeouts completed
- ISM 2.0 target: ~75% domestic self-sufficiency in semiconductor demand by 2030
- ISM governance: independent Business Division of Digital India Corporation, under MeitY