Govt notifies Rs 1.27 lakh crore Semicon 2.0 scheme to boost chip ecosystem
The government notified the Semicon 2.0 scheme (India Semiconductor Mission 2.0) with a total outlay of Rs 1.27 lakh crore (Rs 1,27,500 crore) to strengthen India's semiconductor manufacturing and design ecosystem
The scheme provides fiscal support across the complete semiconductor value chain, from chip design and fabrication to packaging, testing, equipment, and materials
Support has been structured across six segments: chip design, semiconductor manufacturing equipment and materials, fabrication units (fabs), assembly-testing-marking-packaging (ATMP/OSAT), research and development, and talent development
The scheme prioritises "resilient, trusted, and sovereign" semiconductor technologies, including indigenous IP cores, chips, SoCs, and modules for strategic national infrastructure
The notification follows Cabinet approval of the India Semiconductor Mission (ISM) 2.0 outlay, expanding on the earlier Rs 76,000 crore ISM 1.0 approved in December 2021
India Semiconductor Mission (ISM) — Institutional Architecture
The India Semiconductor Mission is the nodal agency for implementing India's semiconductor and display fab incentive schemes, functioning under the Ministry of Electronics and Information Technology (MeitY). It was constituted as an Independent Business Division within Digital India Corporation to design and execute schemes for the semiconductor and display ecosystem.
Semicon 2.0 is the second, larger phase of the same ISM architecture — widening the incentive net from large fabs to chip-design startups, MSMEs, equipment/materials makers, and training institutes, while roughly 1.7x-ing the fiscal outlay of ISM 1.0.
Incentive Structure — Capex Support Across the Value Chain (Design-Linked Incentive lineage)
Semicon 2.0 fine-tunes capital-expenditure-linked incentives by segment rather than a flat subsidy, reflecting the differing capital intensity of fabrication versus packaging versus design. This differentiated-incentive approach builds on the earlier Design Linked Incentive (DLI) scheme (part of ISM 1.0) that funded semiconductor IP and chip design by domestic startups.
Key Details
- CMOS-based silicon fabs are eligible for financial support of about 40% of capital expenditure (pari-passu); other/compound fabs around 35%
- Advanced packaging (ATMP/OSAT) support is around 35% of capex; conventional packaging around 25%
- Chip-design startups and MSMEs can access seed funding of up to Rs 15 crore (capped at 50% of project cost) along with national EDA tool access and multi-project wafer fabrication services under a Design Infrastructure Support framework
- R&D and talent-development projects can receive support of up to 75% of project cost, subject to conditions
The differentiated capex-support percentages are the operative mechanism by which the Rs 1.27 lakh crore outlay is disbursed — students should distinguish these segment-wise rates rather than treat the scheme as a single flat subsidy.
Semiconductor Manufacturing — Fab vs Fabless vs ATMP/OSAT
UPSC-relevant terminology distinguishes stages of chip production: "fab" (fabrication) refers to the capital-intensive wafer-processing plant that etches circuits onto silicon; "fabless" firms only design chips and outsource manufacturing; ATMP/OSAT (Assembly, Testing, Marking, Packaging / Outsourced Semiconductor Assembly and Test) covers the back-end stage that packages finished dies into usable chips.
Key Details
- India currently has negligible domestic fab capacity; most incentivised projects under ISM 1.0 were in the ATMP/OSAT and compound-semiconductor space, which are less capital-intensive than leading-edge silicon fabs
- Global fab capacity is concentrated in Taiwan (TSMC), South Korea (Samsung), and the US; India's strategy under Semicon 2.0 leans on developing intermediate segments (equipment, materials, packaging, design) while building toward mature-node fabs
- Strategic rationale: reducing import dependence on chips used in defence, telecom, and critical infrastructure ("sovereign" semiconductor technology)
Semicon 2.0's six-segment structure explicitly funds each stage of this value chain separately, aiming to build ecosystem depth (equipment and materials suppliers, design houses, packaging units) around India's still-nascent fab capacity.
- Semicon 2.0 (ISM 2.0) outlay: Rs 1,27,500 crore (~Rs 1.27 lakh crore)
- ISM 1.0 (2021) outlay: Rs 76,000 crore
- Six segments: chip design; equipment and materials manufacturing; fabs; ATMP/OSAT (assembly, testing, packaging); R&D; talent development
- CMOS silicon fab capex support: ~40%; other fabs: ~35% (pari-passu)
- ATMP/OSAT capex support: advanced packaging ~35%, conventional packaging ~25%
- Design-startup seed funding: up to Rs 15 crore, capped at 50% of project cost
- Nodal body: India Semiconductor Mission (ISM), under Ministry of Electronics and Information Technology (MeitY)
- Under ISM 1.0: 12 units approved, ~Rs 1.64 lakh crore cumulative investment; India's first fab expected around 2028