200 startups, 1 lakh technicians, $12 billion investment: Vaishnaw lays out Semicon 2.0 roadmap
The government laid out the roadmap for Semicon 2.0, the second phase of India's semiconductor mission, at the inaugural session of a semiconductor industry event
The roadmap targets at least 200 chip-design startups (up from 105 under the first phase), training of over 1 lakh (100,000) technicians for cleanroom and factory-floor roles within five years, and investment commitments of roughly $11-12 billion to be deployed over the next two to three years
Semicon 2.0 is structured around six pillars: chip design, machines and materials, fabrication facilities (fabs), advanced packaging, research and development, and talent
A global materials and equipment major separately pledged $5 billion under a decade-long India-focused investment initiative, and a domestic conglomerate finalised 16 memoranda of understanding covering wafer production, assembly, testing, packaging, and design services
India Semiconductor Mission (ISM) — Phase 1 vs Phase 2 (Semicon 2.0)
The India Semiconductor Mission was approved by the Union Cabinet on 15 December 2021 with an outlay of ₹76,000 crore, under the Ministry of Electronics and Information Technology (MeitY), as the nodal agency for developing a sustainable semiconductor and display ecosystem in India. Semicon 2.0, approved by the Union Cabinet in July 2026 with a substantially larger outlay of ₹1,27,500 crore (roughly $12 billion), marks a shift from supporting individual fab projects to building a comprehensive value-chain ecosystem covering design, equipment, materials, fabrication, packaging, R&D, and skilled manpower.
Key Details
- ISM Phase 1 (2021): ₹76,000 crore outlay; supported 10-12 approved projects (fabs, compound semiconductor units, assembly/testing/packaging facilities) with cumulative investments exceeding ₹1.6 lakh crore; three projects have since reached commercial production
- Semicon 2.0 (2026): ₹1,27,500 crore outlay; organised around six pillars rather than fab-by-fab incentives
- Nodal ministry for both phases: Ministry of Electronics and Information Technology (MeitY), through the India Semiconductor Mission
- Fiscal support under ISM Phase 1 covered up to 50% of project cost for silicon fabs, compound semiconductor facilities, and ATMP (Assembly, Testing, Marking, Packaging) units
The 200-startup and 1-lakh-technician targets announced are the design and talent components of the six-pillar Semicon 2.0 framework, building on the base established by ISM Phase 1's ₹76,000 crore push.
Design Linked Incentive (DLI) Scheme
The DLI Scheme is a component of the India Semiconductor Mission that provides financial incentives and design infrastructure support to domestic semiconductor design companies across various stages of chip development, including Integrated Circuits (ICs), Chipsets, Systems-on-Chip (SoCs), and IP cores. It is administered by C-DAC (Centre for Development of Advanced Computing) as the nodal implementing agency.
The 200-startup target announced is a direct scale-up commitment for the DLI-supported design ecosystem, positioning chip design (a low-capital, high-skill segment) as a priority alongside capital-intensive fabrication.
Assembly, Testing, Marking and Packaging (ATMP/OSAT) and the Semiconductor Value Chain
Semiconductor manufacturing is divided into front-end (wafer fabrication, requiring the highest capital and technological intensity) and back-end operations — Assembly, Testing, Marking and Packaging (ATMP), also called Outsourced Semiconductor Assembly and Test (OSAT). India's strategy has prioritised back-end and packaging capacity as a faster, less capital-intensive entry point into the global chip value chain before scaling up front-end fabrication.
Key Details
- Advanced packaging is one of the six Semicon 2.0 pillars, reflecting India's comparative entry advantage in back-end operations over front-end fabs
- India currently has under-28nm node fabrication capability under development; the R&D pillar aims to move toward more advanced process nodes
- Talent development targets include cleanroom operations staff, fab-construction workers, and OSAT-specific skills, delivered partly through partnerships with international technical institutes
The six-pillar structure explicitly separates fabs from advanced packaging, signalling that Semicon 2.0 treats OSAT/ATMP capacity building as a distinct, parallel priority rather than a byproduct of fab investment.
- Semicon 2.0 outlay: ₹1,27,500 crore (approximately $12 billion), approved by the Union Cabinet in July 2026
- ISM Phase 1 (December 2021) outlay: ₹76,000 crore
- Chip-design startup target: at least 200 (up from ~105 under Phase 1); ~20-24 have secured VC funding worth ~₹800 crore
- Technician training target: over 1 lakh (100,000) within five years, covering cleanroom and factory-floor roles
- Six Semicon 2.0 pillars: chip design, machines and materials, fabs, advanced packaging, R&D, talent
- Nodal ministry: Ministry of Electronics and Information Technology (MeitY), via the India Semiconductor Mission