Semicon 2.0: Govt notifies ₹1.27 lakh crore scheme to boost chip ecosystem
The Union Government notified "Semicon 2.0," a scheme with a total outlay of about ₹1.27 lakh crore to strengthen India's semiconductor ecosystem.
The scheme is structured across six segments spanning the semiconductor value chain: chip design by domestic firms, capital equipment for chip manufacturing, semiconductor fabrication (fabs), and assembly, testing, marking and packaging (ATMP/OSAT) facilities, among others.
The stated objective is to build resilient, trusted, and sovereign semiconductor capability, with fiscal support targeted at local development of semiconductor IP cores, chips, System-on-Chips (SoCs), and modules identified as strategically important.
A high-level chip panel was announced alongside the scheme notification to guide implementation.
India Semiconductor Mission (ISM) — Origins and Evolution to Semicon 2.0
The India Semiconductor Mission was launched in December 2021 with an outlay of ₹76,000 crore as the government's flagship programme to build a domestic chip design, fabrication, and packaging ecosystem, offering fiscal support of up to 50% of project cost for silicon fabs, compound semiconductor units, and assembly/testing facilities. Semicon 2.0 extends and broadens this original mission with an even larger corpus and a more granular six-segment structure covering the fuller value chain, including capital equipment manufacturing — a segment largely absent from the original scheme's direct incentive structure.
Semicon 2.0 is presented as "2.0" precisely because it deepens and widens ISM 1.0 — moving from a scheme focused mainly on anchoring the first few fabs/ATMP units to one that fills in upstream gaps (capital equipment) and downstream depth (design, packaging) across the full value chain.
Design Linked Incentive (DLI) Scheme and Chip Design
The Design Linked Incentive (DLI) scheme, launched alongside ISM in December 2021 with an outlay of ₹1,000 crore, supports Indian semiconductor design start-ups and companies through product-development incentives (reimbursing a share of eligible expenditure) and deployment incentives (linked to actual sales of the designed chip), aiming to build indigenous chip design IP rather than only manufacturing capacity.
Key Details
- DLI is distinct from manufacturing-linked incentives — it targets the "fabless" design segment of the industry, where a firm designs chips but outsources fabrication.
- Semicon 2.0's chip-design segment builds on the DLI's foundation, continuing support for design-linked incentives as one of the scheme's six pillars.
- India's fabless chip design talent pool is considered a comparative strength, even as fabrication capacity is still being built domestically.
One of Semicon 2.0's six notified segments explicitly covers "designing of chips by Indian firms" — a direct continuation of the DLI-driven push to build design capability, now folded into the larger scheme's architecture.
Production Linked Incentive (PLI) Schemes — Broader Context
The Production Linked Incentive (PLI) scheme is a broader Government of India instrument (first introduced in 2020 for sectors like mobile manufacturing and later extended to 14 sectors) that offers financial incentives to companies based on incremental sales/production of goods manufactured domestically, aimed at boosting domestic manufacturing, reducing import dependence, and creating economies of scale for global competitiveness. In semiconductors, the PLI-style incentive model (offering up to 50% fiscal support for fabs) was adapted specifically for capital-intensive chip manufacturing rather than the sales-linked PLI model used in sectors like electronics or pharma.
Semicon 2.0 continues this PLI-style, high-percentage capital subsidy model rather than a sales-linked incentive, reflecting the reality that global semiconductor investment decisions are driven primarily by capital cost offsets, not production targets.
- Semicon 2.0 outlay: approximately ₹1.27 lakh crore (₹1.27 trillion).
- Original India Semiconductor Mission (ISM): launched December 2021 with ₹76,000 crore outlay.
- Design Linked Incentive (DLI) scheme: launched December 2021 with ₹1,000 crore outlay, targeting fabless chip design start-ups.
- Under ISM 1.0, six semiconductor/display fab and ATMP projects were approved with combined committed investment exceeding ₹1.6 lakh crore.
- Major approved projects include Tata Electronics-PSMC's fab at Dholera, Gujarat (~₹91,000 crore) and Micron Technology's ATMP facility at Sanand, Gujarat (over ₹22,500 crore).
- Semicon 2.0 is structured across six segments: chip design, capital equipment for chip production, semiconductor fabs, and chip assembly, packaging, and testing (among the six).