Cabinet clears India Semiconductor Mission 2.0 with ₹1.27 lakh crore outlay
The Union Cabinet approved Semicon 2.0, the second phase of the India Semiconductor Mission, with a budget outlay of ₹1.27 lakh crore.
The programme is structured around six pillars covering the full semiconductor value chain: chip design, semiconductor equipment and materials, fabrication capacity, Assembly, Testing, Marking and Packaging (ATMP)/Outsourced Semiconductor Assembly and Test (OSAT), advanced research and development, and talent development.
The government stated the objective is to strengthen economic growth, build resilient supply chains for national security, and establish technological leadership in critical industries.
The Ministry of Electronics and Information Technology (MeitY) remains the nodal ministry, implementing the mission through the India Semiconductor Mission body housed in the Digital India Corporation.
Semicon 1.0 — What the First Phase Achieved
The first phase of the India Semiconductor Mission (approved 15 December 2021, outlay ₹76,000 crore) sanctioned 12 manufacturing projects with cumulative committed investment exceeding ₹1.64 lakh crore. This included India's first silicon fab, first silicon carbide compound-semiconductor fab, an integrated gallium nitride Micro LED display fab, and nine ATMP/OSAT packaging units, spread across states such as Gujarat and Assam.
Key Details
- Semicon 1.0 approved: 15 December 2021; outlay ₹76,000 crore
- 12 projects approved; combined committed investment over ₹1.64 lakh crore
- India's first commercial semiconductor fab is scheduled for commissioning in 2028
- Three companies have already begun commercial production of packaged chips under Semicon 1.0, with another expected to become operational in 2026
Semicon 2.0 is explicitly designed to build on this base — moving from "getting the first fabs and packaging units approved" to a fuller value chain that also covers design, upstream materials, and R&D beyond current technology nodes.
Chip Fabrication Nodes — Mature vs Advanced Technology
Semiconductor fabrication is classified by "node size" (measured in nanometres), which broadly indicates transistor density and chip performance. India's current fab and packaging ecosystem operates mainly in mature/legacy nodes (28nm to 110nm), used for automotive, power, and telecom chips, while advanced nodes (below 10nm, down to 2–3nm) power high-end smartphones, AI accelerators, and data-centre processors and remain concentrated in Taiwan, South Korea, and the US.
Key Details
- India's current commissioned/under-construction fab capacity spans the 28nm–110nm mature-node range
- Advanced-node (sub-10nm) fabrication requires extreme ultraviolet (EUV) lithography, a technology India does not yet possess domestically
- Semicon 2.0's R&D pillar is explicitly framed as building capability "beyond current nodes," signalling an eventual move toward more advanced fabrication
- Global fab capacity for advanced nodes is dominated by TSMC (Taiwan) and Samsung (South Korea)
By adding a dedicated R&D pillar, Semicon 2.0 acknowledges that India's mature-node focus under Semicon 1.0 addresses only part of global chip demand, and signals a longer-term ambition to move up the technology ladder.
Semiconductor Talent Ecosystem and Design Startups
Chip design (the "fabless" segment) is capital-light relative to fabrication and is an area where India already has a large pool of engineering talent employed by multinational chip design centres. The talent-development pillar of Semicon 2.0 builds on this base by expanding Electronic Design Automation (EDA) tool access in universities.
Key Details
- 315 universities currently provide chip-design training using industry-standard EDA tools, with roughly 68,000 students trained so far
- 105 startups are currently engaged in chip design work, spanning both strategic (defence/space) and commercial applications
- The Design Linked Incentive (DLI) Scheme, launched alongside Semicon 1.0 in December 2021, remains the primary financial support mechanism for design startups (up to 50% reimbursement of eligible expenditure, capped at ₹15 crore per application)
Semicon 2.0's design and talent pillars aim to convert India's existing design-workforce advantage into higher domestic intellectual-property ownership, rather than India remaining primarily a services location for foreign semiconductor design work.
- Semicon 2.0 outlay: ₹1.27 lakh crore (≈ ₹1,27,500 crore)
- Semicon 1.0 outlay (December 2021): ₹76,000 crore; 12 projects; over ₹1.64 lakh crore committed investment
- Six pillars: design ecosystem, equipment/materials, fabrication capacity, ATMP/OSAT, advanced R&D, talent development
- Universities with EDA-based chip design training: 315; students trained: ~68,000
- Chip-design startups currently active: 105
- India's first semiconductor fab commissioning target: 2028
- Nodal ministry: Ministry of Electronics and Information Technology (MeitY); implementing body: India Semiconductor Mission under Digital India Corporation