← Resources · August 31, 2026
Economics GS3 3 min read

Govt notifies ₹1,27,500-crore Semicon 2.0; spells out eligibility norms, sops for chip ecosystem

What happened
01

The government formally notified Semicon 2.0, a semiconductor incentive scheme with an outlay of ₹1,27,500 crore, laying out eligibility norms and support structures for the chip ecosystem

02

The scheme covers six segments of the semiconductor value chain: chip design, capital equipment manufacturing, semiconductor fabrication, compound/photonics/sensor fabs, materials, and assembly-testing-packaging

03

Financial support for startups will be structured as grants and equity co-investment, while established companies will receive support through royalty financing or equity co-investment

04

Eligibility thresholds are segment-specific: CMOS silicon fabs need a minimum capex of ₹1,000 crore (get 40% capex support); compound semiconductor/photonics/sensor fabs need ₹500 crore minimum investment (35% capex support); equipment R&D facilities need ₹300 crore minimum investment

05

The notification follows Cabinet approval of the scheme's outlay in mid-2026

Static topic 1 of 3 · Economics

India Semiconductor Mission (ISM) — Origin and Evolution

The India Semiconductor Mission was launched in December 2021 under the broader "Semicon India Programme" with an initial incentive outlay of ₹76,000 crore, offering fiscal support of up to 50% for silicon fabs, compound semiconductor facilities, assembly/testing units, and chip design. ISM is housed as an Independent Business Division within the Digital India Corporation, under the Ministry of Electronics and Information Technology (MeitY). Semicon 2.0 is the scheme's expanded second phase, widening coverage across the value chain and adjusting capex support ratios by segment.

Connection to this news

Semicon 2.0 is the notified, operational successor to the original ISM framework — the eligibility norms just released convert the Cabinet's outlay approval into segment-wise investment and revenue thresholds that companies must meet to claim incentives.

Static topic 2 of 3 · Economics

Design Linked Incentive (DLI) Scheme

The DLI Scheme, launched alongside ISM in December 2021, targets the chip design segment specifically — offering financial and infrastructural support to startups, MSMEs, and established companies designing ICs, chipsets, and Systems-on-Chip (SoCs). It aims to develop 100 domestic semiconductor design companies and help at least 20 scale to revenues above ₹1,500 crore within five years.

Connection to this news

Semicon 2.0's "chip design by Indian companies" segment builds on the DLI Scheme's foundation, extending grant and equity co-investment support specifically to startups in this category.

Static topic 3 of 3 · Economics

Semiconductor Value Chain Segmentation (Fab vs ATMP vs Design)

UPSC-relevant distinctions in the semiconductor industry: Fabrication (Fab) — the capital-intensive process of manufacturing chips on silicon wafers; ATMP (Assembly, Testing, Marking, Packaging) — downstream processes converting fabricated wafers into usable chips, far less capital-intensive than fabs; Design — the IP-creation stage (chip architecture, SoCs), least capital-intensive but high value-addition. India's strategy under Semicon 2.0 spans all three, unlike the initial ISM phase which was more fab-centric.

Key Details

  • Fabs require the highest capex thresholds (₹500 crore–₹1,000 crore minimum under Semicon 2.0)
  • ATMP and testing facilities have lower entry thresholds (e.g., ₹100 crore for test/characterisation facilities)
  • India currently has committed fab and ATMP projects in Gujarat (Dholera, Sanand) and Assam (Morigaon)
Connection to this news

The tiered eligibility structure notified under Semicon 2.0 reflects this value-chain segmentation, calibrating support intensity to the capital risk of each stage.

Key facts & data
  • Semicon 2.0 total outlay: ₹1,27,500 crore
  • Original ISM (2021) outlay: ₹76,000 crore
  • CMOS silicon fab minimum capex: ₹1,000 crore; capex support: 40%
  • Compound semiconductor/photonics/sensor fab minimum capex: ₹500 crore; capex support: 35%
  • Equipment R&D facility minimum investment: ₹300 crore, revenue ₹120 crore
  • Semiconductor-grade materials facility minimum investment: ₹50 crore, revenue ₹20 crore
  • Test and characterisation facility minimum investment: ₹100 crore, revenue ₹40 crore
  • Nodal body: India Semiconductor Mission (ISM), under MeitY
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